The present invention relates to an error correcting encoder/decoder for an installation using digital transmission, in particular by radio beam.
The purpose of using error correcting encoding in the digital radio beams used for civilian transmission is to correct isolated errors that come, for example, from the ignition systems of motor vehicles.
In order to reduce inter-channel disturbances as much as possible, the increase in data rate due to the error-correcting encoding should not exceed about 3% of the initial data rate due to multiplexing the main data flow with additional operating and maintenance information and with other data streams, if any. It is only under this condition that the filter characteristics of the transmission system in equipment existing prior to the introduction of the encoding can be conserved: it is then possible to change from a non-coded version to an encoded version of the equipment merely by swapping the frame-cards, only. In such applications it is therefore appropriate to select from the numerous error correcting codes that exist in the literature an error correcting code which is simple and has a low redundancy rate.
In addition, in this type of application, it is advantageous to use an error correcting code which is ipso facto transparent to phase ambiguity (which is manifested, as is known, by the fact that the twos complement of a code word also belongs to the code).
Finally, it is advantageous for the selected error correcting code to be capable of being applied to all radio beams, regardless of the type of modulation used: having 4, 16, 64 or even 256 phase states.
All of these constraints have lead the inventors to select the Wyner-Ash code from amongst the error correcting codes which exist in the literature.
This code is as described, for example, in the work of the Russian author Alexandru Spataru "Fondements de la theorie de la transmission de l'information" (Fundamentals of information transmission theory), published in France by Presses Polytechniques Romandes, 1987, pp. 132-136.
It is a systematic convolutional code which enables one error, and one error only, to be corrected in the entire constraint length, regardless of the position the error occupies in a block.
Its three parameters, namely: k (number of information bits input to the encoder); n (number of output bits from the encoder); and m (order of the delay memory included in the encoder), are defined by the following equations: EQU k=2p-1 EQU n=k+1 EQU m=p+1
where p is an integer.
In the case under consideration, it is explained above that the redundancy rate of the code should not be significantly greater than 3%, thereby limiting suitable values for the number p. Calculation shows that under these conditions it is necessary to select an integer p which is not less than 5. In particular, if p is selected to be equal to 5, then a code is obtained for which k=31 and n=32, thereby giving an acceptable redundancy rate of 3.2%.
This code is such that the check bit Yi of an n-bit block leaving the encoder at instant i is calculated as a function of the k other bits in the same block at said instant i (Xi,1; Xi,2; Xi,3; . . . ; Xi,k), as a function of the same k other bits at the instant i=1 (Xi-1,1; Xi-1,2; . . . , Xi-1,k), etc. . . . , and finally as a function of the same k other bits at the instant i-m (Xi-m,1; . . . ; Xi-m,k), by performing modulo-2 addition of all of the k other bits present at the instants: i, i-1, . . . , i-m; and each weighted by a respective coefficient A which is equal to 0 or to 1, and which is defined by the code generator matrix.
For greater clarity, this method of calculating the check bit Yi is shown diagrammatically in accompanying FIG. 1. In this diagram, the k bits (Xi,1; Xi,2; . . . , Xi,k) entering the encoder at instant i are placed on the left of the figure whereas the (k+1) bits (Xi,1; Xi,2; . . . ; Xi,k; Yi) leaving it at the same instant i are on the right of the figure.
The check bit Yi is the output from a binary adder S1 which itself receives the k input bits, each weighted by a respective coefficient A1,1; A1,2; . . . , A1,k, each of which is equal to 1, and which also receives the output from a counting bistable B2.
The counting bistable B2 itself receives the output from another binary summing circuit S2. The inputs of this summing circuit S2 are themselves constituted firstly by the k input bits, each weighted by a respective coefficient A2,1; A2,2; . . . ; A2,k equal to 0 or to 1 and defined by the code generator matrix, and secondly the output from another counting bistable B3, and so on to the "modulo-2" adder Sm whose output is applied to counting bistable Bm, and whose input receives only the k predefined input bits, each weighted by a respective coefficient Am,1; Am,2; . . . ; Am,k, where each coefficient is equal to 0 or 1 and is defined by the code generator matrix, which matrix is thus as follows:
______________________________________ R1 = A1,1 A1,2 . . . A1,k R2 = A2,1 A2,2 . . . A2,k . . . . . . Rm = Am,1 Am,2 . . . Am,k ______________________________________
it being understood that the coefficients in the first row R1 of the matrix (A1,1 to A1,k) are all equal to 1.
In order to apply this encoding principle directly to digital transmissions by radio beam, it would be necessary to provide serial-to-parallel conversion upstream from the encoder and parallel-to-serial conversion downstream from the encoder, since the Wyner-Ash encoder is a priori a parallel encoder, as can clearly be seen from FIG. 1. This would suffer from the drawback of complicated and expensive physical implementation.
The invention seeks to remedy this drawback.